This invention relates generally to microprocessors, and, more specifically, to the control of memory and input-output devices from a microprocessor integrated circuit.
In current computer systems, a microprocessor, usually formed on a single integrated circuit chip, communicates with random access memory (RAM) and input-output (I/O) devices formed on separate integrated circuit chips. In response to program instructions, the microprocessor controls reading from or writing to system RAM and I/O devices over a common system bus. Read and write control signals are communicated from the microprocessor to all such RAM and I/O devices in a computer system. An addressed device or portion of a device then responds by executing a read or write instruction with appropriate timing provided by the respective read or write control signal. Different standard control signal protocols are utilized. Additional logic external of the microprocessor, RAM and I/O devices is often required in order to convert between protocols or provide a device, such as a memory device, with the exact timing signals that it requires for operation in the system. The situation is similar with respect to other control signals, such as interrupt signals, interrupt acknowledge, wait, and so forth.
Therefore, it is a primary object of the present invention to provide a microprocessor capable of directly providing to other circuit chips, such as RAM and I/O devices, the exact control timing signals they require.
It is another object of the present invention to minimize the amount of logic required external of the principal system integrated circuit chips in order to properly communicate control and status signals between them.
It is also an object of the present invention to provide control and status signals that allow various memory and input-output devices to execute transactions with the system bus at the maximum rate possible for those devices.